During the manufacturing of a semiconductor device, as a patterning technology for forming circuit patterns on a semiconductor wafer (hereinafter, simply referred to as a ‘wafer’) that is a substrate to be processed, photolithography has been used. Since the semiconductor device is becoming highly integrated in terms of improving the operating speed, the patterning technology using the photolithography has required the circuit patterns formed on the wafer to be fine. For this reason, although the wavelength of light used for exposure has been traditionally shortened, it cannot be sufficiently applied to an ultra-fine semiconductor device after 45 nm node.
As the patterning technology applicable for the ultra-fine semiconductor device after 45 nm node, a technology has been proposed performing a patterning process (e.g., formation of a resist film, exposure, heat treatment, developing) several times using the photolithography so as to form a pattern of a single layer. See, for example, Japanese Patent Application Laid-Open No. H07 (1995)-147219. In this case, a technology of performing the patterning process twice is referred to as a double patterning. As one technology of the double patterning, there is lithography-lithography-etching (LLE). The LLE performs a first patterning to form a first resist pattern, performs a second patterning to form a second resist pattern, and performs an etching process using a fine mask pattern formed of the first and second resist patterns.